Class notes from Thursday, February 22

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Exercise: add these two 8-bit binary numbers

  11   11  <-- carry bits
  00101001  (41)
+ 01110011 (115)
----------
  10011100 (156)

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We can represent 2^N distinct numbers in an N-bit register

Unsigned representation:

00000000   0
00000001   1
00000010   2
...
01111101   125
01111110   126
01111111   127
10000000   128
10000001   129
10000010   130
...
11111101   253
11111110   254
11111111   255

What about negative numbers?

Sign/magnitude representation:

00000000   0      <-- positive zero
00000001   1
00000010   2
...
01111101   125
01111110   126
01111111   127
10000000   -0     <-- negative zero
10000001   -1
10000010   -2
10000011   -3
...
11111101   -125
11111110   -126
11111111   -127

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Two's Complement Representation

00000000   0
00000001   +1
00000010   +2
00000011   +3
...
01111101   +125
01111110   +126
01111111   +127
10000000   -128
10000001   -127
10000010   -126
10000011   -125
...
11111101   -3
11111110   -2
11111111   -1

Leftmost bit indicates sign

Notice that there is no +128

To decode a negative number (leading 1), just complement it and add 1,
and discard any leftover carry.  This way, zero (00000000) becomes its
own complement, and we have only one representation for zero.

11111110 (-2) => 00000001 + 1 = 00000010 (+2)
11111111 (-1) => 00000000 + 1 = 00000001 (+1)
00000000 (0)  => 11111111 + 1 = 00000000 (0)
00000001 (+1) => 11111110 + 1 = 11111111 (-1)
00000010 (+2) => 11111101 + 1 = 11111110 (-2)

10000001 (-127) => 01111110 + 1 => 01111111 (+127)
00000000 (0)    => 11111111 + 1 => 00000000 (0)
11111111 (-1)   => 00000000 + 1 => 00000001 (+1)
00000001 (+1)   => 11111110 + 1 => 11111111 (-1)

Special case: negating -128 gives -128

10000000 (-128) => 01111111 + 1 => 10000000 (-128)

This is because there is no valid two's complement representation
of +128 using eight bits.

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What happens if we add these numbers in two's complement?

 011   11  <-- carry bits
  ^carry in column
 ^carry out column
  00101001  (41)
+ 01110011 (115)
----------
  10011100 (-100, not 156)

Above, carry in = 1, carry out = 0  =>  OVERFLOW CONDITION (error)

How can we build a computer circuit to detect overflow?
   carry in equals carry out  =>  no problem
   00000000 (0)    => 11111111 + 1 => 00000000 (0)    (cIn = 1, cOut = 1)
   10000001 (-127) => 01111110 + 1 => 01111111 (+127) (cIn = 0, cOut = 0)

   carry in does not equal carry out  =>  OVERFLOW!
   10000000 (-128) => 01111111 + 1 => 10000000 (-128) (Cin = 1, Cout = 0)

How can we build a computer circuit to do binary addition?

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Introduction to Boolean logic

- only two possible values: True and False
- three basic operations:
  a AND b      a OR b       NOT a
- a and b represent True/False ("boolean") values

Truth tables explain how AND/OR/NOT work:

a   b    a AND b    a OR b
--------------------------
F   F      F          F
F   T      F          T
T   F      F          T
T   T      T          T

a   NOT a
---------
F    T
T    F

a   b    a XOR b    a NAND b   a NOR b
--------------------------------------
F   F      F          T           T
F   T      T          T           F
T   F      T          T           F
T   T      F          F           F

Example: Suppose a = True, b = False, and c = True
Value of   (a AND (NOT c)) OR b   is False

Exercise: construct truth tables for
  - (NOT (a AND b))
  - (NOT a) OR (NOT b)
  - ((NOT a) AND b) OR (a AND (NOT b))

equivalent to "a NAND b" and "a XOR b"

de Morgan's laws:
NOT (a AND b) = (NOT a) OR (NOT b)
NOT (a OR b)  = (NOT a) AND (NOT b)

Draw circuit diagram for (a AND (NOT c)) OR b

Draw circuit diagram for XOR

a EQUALS b = (NOT (a XOR b))

This can be used to test if carry in equals carry out in an adder circuit.